Convert your verilogs to VHDL format in no time at all
This utility has been developed for those who wants to convert an existing verilog design into VHDL. The generated VHDL may not work as is and may require minor manual correction in order to ensure the VHDL data type matching. This has been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file.
Requirements:
• Java
Operating system:Windows 8, Windows 7, Windows Vista, Windows XP, Windows 2000, Windows 98
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Verilog to VHDL Converter 11 APR 2013 
